The invention relates to a circuit having a clock signal synchronizing device, in one embodiment a delayed locked loop (DLL) with capability to filter clock-jitter. Further, the invention relates to a clock signal synchronizing method with capability to filter clock-jitter.
A conventional DLL may—as is illustrated in FIG. 1—e.g., includes a phase detector 11, a variable delay element 12, and a constant delay element 15.
An incoming clock signal is received at an input of the variable delay element 12, delayed by a variable delay of the latter, relayed to the constant delay element 15, delayed by a constant delay of the latter, and then forwarded to the phase detector 11. The phase detector 11 compares the phase of the incoming clock signal received at a first input of the phase detector 11 with the delayed clock signal received from an output of the constant delay element 15 at a second input of the phase detector 11. If the two received clock signals are not in phase, the phase detector 11 adjusts the variable delay of the variable delay element 12, i.e., increases the variable delay by a predetermined process. In other cases, the phase detector 11 may decrease the variable delay by a predetermined process.
Then, a new cycle begins and the incoming clock signal is delayed by the adjusted variable delay of the variable delay element 12 and the constant delay of the constant delay element 15 and is then relayed to the second input of the phase detector 11. The phase detector 11 compares the received delayed clock signal with the incoming clock signal and, again, adjusts the variable delay of the variable delay element 12, i.e., increases (or decreases) the variable delay by a predetermined process if the two clock signals are not in phase. Then again, a new cycle begins and the process is iterated until the DLL is “locked”, i.e. the incoming clock signal and the delayed clock signal which is the outgoing clock signal are in phase.
It is noted that the phase detector 11 either increases the variable delay in each cycle until the two clock signals at its input are in phase or decreases the variable delay in each cycle until the two clock signals are in phase.
Thus, it is guaranteed that the DLL locks after a certain maximum of cycles at the latest, the maximum being the period of the incoming clock signal divided by the predetermined process for adjusting the variable delay of the variable delay element 12.
Therefore, a DLL requires only a rather short period of time to reach a “locked state”, i.e. the incoming and outgoing clock signals are in phase. However, if the incoming clock signal includes clock-jitter the clock-jitter of the incoming clock signal will be directly transferred to the outgoing clock signal. Such clock-jitter can severely degrade the quality of outgoing data since the falling and rising edges of a read-data-eye during which outgoing data is to be transmitted will become blurred.
In contrast to a conventional DLL, a phase lock loop (PLL) is capable of filtering clock-jitter of an incoming clock signal. However, a PLL requires a substantially longer period of time to reach a “locked state”.
Therefore, there e.g., exists a need for a clock signal synchronizing device which both filters clock-jitter of an incoming clock signal and requires only a short period of time to reach a “locked state”.
For these or other reasons, there is a need for the present invention.